Feng-Jun Li, Jing-Fu Bao, Hong-Yun Huang, Shao-Chun Jin. A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System[J]. Journal of Electronic Science and Technology, 2012, 10(4): 358-362. DOI: 10.3969/j.issn.1674-862X.2012.04.012
Citation: Feng-Jun Li, Jing-Fu Bao, Hong-Yun Huang, Shao-Chun Jin. A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System[J]. Journal of Electronic Science and Technology, 2012, 10(4): 358-362. DOI: 10.3969/j.issn.1674-862X.2012.04.012

A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

doi: 10.3969/j.issn.1674-862X.2012.04.012
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This work was supported by the Circuit and System Foremost Discipline of Zhejiang Province under Grant No. ZZ050103-11.

More Information
  • Received Date: 2012-04-07
  • Rev Recd Date: 2012-05-15
  • Publish Date: 2012-12-24
  • At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency (RF) power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response (FIR) linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion (DPD) system based on this algorithm achieves good performance.
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