FPGA-based acceleration for binary neural networks in edge computing

Jin-Yu Zhan; An-Tai Yu; Wei Jiang; Yong-Jia Yang; Xiao-Na Xie; Zheng-Wei Chang; Jun-Huan Yang

doi:10.1016/j.jnlest.2023.100204

Jin-Yu Zhan, An-Tai Yu, Wei Jiang, Yong-Jia Yang, Xiao-Na Xie, Zheng-Wei Chang, Jun-Huan Yang. FPGA-based acceleration for binary neural networks in edge computingJ. Journal of Electronic Science and Technology, 2023, 21(2): 100204. DOI: 10.1016/j.jnlest.2023.100204

Citation:

Jin-Yu Zhan, An-Tai Yu, Wei Jiang, Yong-Jia Yang, Xiao-Na Xie, Zheng-Wei Chang, Jun-Huan Yang. FPGA-based acceleration for binary neural networks in edge computingJ. Journal of Electronic Science and Technology, 2023, 21(2): 100204. DOI: 10.1016/j.jnlest.2023.100204

Citation:

Jin-Yu Zhan, An-Tai Yu, Wei Jiang, Yong-Jia Yang, Xiao-Na Xie, Zheng-Wei Chang, Jun-Huan Yang. FPGA-based acceleration for binary neural networks in edge computingJ. Journal of Electronic Science and Technology, 2023, 21(2): 100204. DOI: 10.1016/j.jnlest.2023.100204

FPGA-based acceleration for binary neural networks in edge computing

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