Shyue-Kung Lu, Wei-Yuan Liu. Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain[J]. Journal of Electronic Science and Technology, 2009, 7(4): 291-296.
Citation: Shyue-Kung Lu, Wei-Yuan Liu. Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain[J]. Journal of Electronic Science and Technology, 2009, 7(4): 291-296.

Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

More Information
  • Author Bio:

    Shyue-Kung Lu research interests are in the areas of VLSI testing and fault-tolerant computing, video coding techniques and architectures design, sklu@ee.ntust.edu.tw;
    Wei-Yuan Liu, wyliu@mail.fju.edu.tw

    Shyue-Kung Lu research interests are in the areas of VLSI testing and fault-tolerant computing, video coding techniques and architectures design, sklu@ee.ntust.edu.tw;
    Wei-Yuan Liu, wyliu@mail.fju.edu.tw

  • Rev Recd Date: 2009-09-22
  • Publish Date: 2009-12-24
  • Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array (ILA) of processing elements (PEs) and multiplying elements (MULs). The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.
  • Catalog

      Article Metrics

      Article views (414) PDF downloads (38) Cited by()
      Related
      Proportional views

      /

      DownLoad:  Full-Size Img  PowerPoint
      Return
      Return